Method for producing a transistor structure

ABSTRACT

A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

The present invention relates to a method for fabricating a transistorstructure, comprising at least a first and a second bipolar transistorhaving different collector widths. Such a method is known from DE 100 44838 C2 for example.

In bipolar transistors, the collector is usually terminated by a highlydoped buried layer. The buried layer is produced by subjecting thesubstrate to an ion implantation at the desired location. Afterward, alightly doped epitaxial layer is applied and the wells for base, emitterand collector are produced. A possible process sequence is described forexample in the textbook “Technologie hochintegrierter Schaltungen”[“Technology of large scale integrated circuits”] by D. Widmann, H.Mader, H. Friedrich, Springer Verlag, 2nd edition, Table 8.13, pp.326-334.

For integrated high-frequency circuits in the GHz range, it is favorableto integrate both high-voltage transistors (HV transistor) having a highbreakdown voltage and high-frequency transistors (HF transistors) havinga short collector transit time and hence a high limiting frequencyF_(t). On account of the fabrication methods known heretofore, it isnecessary to find a compromise with regard to the properties in theintegration of bipolar transistors having different limiting frequenciesand bipolar transistors having different breakdown voltages inhigh-frequency circuits. This means that the performance of such ahigh-frequency circuit cannot be utilized optimally.

Such integration has been realized hitherto e.g. by means of thecollector region having a dopant concentration of differing magnitude.The lower the doping, the higher the collector-base breakdown voltage.However, as a result of this the collector transit time becomes longerand hence the limiting frequency F_(t) becomes lower. The higher thedoping, the shorter the collector transit time but the smaller thecollector-base breakdown voltage of the transistor.

M. Racanelli et al. “Ultra High Speed SiGe NPN for Advanced BiCMOSTechnology”, 2001 IEEE discloses scaling the doping of a collectorregion of a transistor in such a way that the dopant concentrationwithin the collector region has a gradient. Although this solution makesit possible to increase the breakdown voltage of HF transistors, itstill represents a compromise.

In addition to the dopant concentration, the dimensioning of thecollector width also determines the properties of a bipolar transistor.The term collector width denotes that region of the epitaxial layerwhich is located between the base well located in the epitaxial layerand the buried layer. HF transistors which are to be optimized towardhigh limiting frequencies must have a small collector width and HVtransistors which are optimized toward high breakdown voltages must havea large collector width.

DE 100 44 838 C2 describes a semiconductor component and also a methodfor fabricating it in which bipolar components having differentcollector widths are realized. In this case, an additional substance isintroduced into a buried layer of a bipolar component, which additionalsubstance influences the diffusion of a dopant of the buried layer andhence the collector width of said bipolar component. However, thismethod does not result in a sharp junction between the differently dopedburied layers and collectors. Consequently, the collector width cannotbe established exactly and with a sharp profile, but rather exhibits a“blurred” profile with a shallow gradient.

Accordingly, it is an object of the present invention to specify anoptimized method for fabricating a transistor structure in whichcollector regions having different collector widths can be formed, thecollector regions having a sharp boundary with respect to the buriedlayers.

According to the invention, the object is achieved by means of a methodof the type mentioned in the introduction in which there are produced atleast a first collector region having a first collector width C1 on afirst buried layer and a second collector region having a secondcollector width C2 on a second buried layer, in which case, for theproduction of the second collector width C2, a first collector zonehaving a first thickness C3 is produced on the second buried layer and asecond collector zone having a second thickness C4 is produced on thefirst collector zone, and at least one insulation region is produced,which isolates at least the collector regions from one another.

What is achieved as a result of this is that the two bipolar transistorsof the transistor structure have a different collector width, and thecollector regions have a sharp or abrupt junction with a steep gradientwith respect to the adjacent regions, such as the buried layers. Thecollector width C1 of the first bipolar transistor preferablycorresponds to the first thickness C3 of the second collector region.The collector width C2 of the second bipolar transistor is composed ofthe thicknesses C3 and C4 of the collector zones of the second collectorregion. Accordingly, the thicker the second thickness C4, the greateralso the difference between the collector widths of the two bipolartransistors.

The invention is based on the insight that a sharp boundary or an abruptjunction between the lightly doped collector and the highly doped buriedlayer significantly improves the behavior of a transistor since anabrupt profile with a steep gradient, with a sheet resistance remainingthe same, has lower fringing capacitances than a profile with a shallowgradient. Equally, the method according to the invention improves thehigh-current behavior of the transistor since there is no unnecessarydopant in that part of the collector which is flooded with chargecarriers and, by the same token, the conduction of the buried layer islowered.

According to the invention, the method of the type mentioned in theintroduction is developed further to the effect that at least a firstzone of a first buried layer of a first conductivity type of the firstbipolar transistor and a first zone of a second buried layer of a firstor a second conductivity type of the second bipolar transistor areintroduced into the semiconductor substrate, a first epitaxial layer isproduced, which covers, over the whole area, at least the first zone ofthe buried layers, at least a second zone of the first conductivity typeis produced within the first epitaxial layer, the second zone adjoiningthe first zone of the first buried layer, a second epitaxial layer isproduced, which covers, over the whole area, at least the firstepitaxial layer and the second zone of the first buried layer, at leastone insulation region is produced, which isolates at least the collectorregions from one another, the second zone of the first buried layeradjoining the first collector region and the first zone of the secondburied layer adjoining the second collector region.

Buried layers having different thicknesses are thereby produced, thethickness of the first buried layer being composed of a first zone,which is introduced into the semiconductor substrate, and a second zone,which is introduced into the first epitaxial layer. The second buriedlayer and the first zone of the first buried layer preferably have thesame thickness in this case. The thicknesses of the first and secondburied layers thus differ by the thickness of the second zone of thesecond buried layer. Since the collector width, as mentioned in theintroduction, depends on the thickness of the epitaxial layer, minus theburied layer extending into the epitaxial layer, the collector widths C1and C2 can be varied in a simple manner and, unlike in embodiments knownhitherto, nevertheless have a sharp junction between the highly dopedburied layers and the lightly doped collector regions.

The inventors furthermore propose developing the method of the typementioned in the introduction further in such a way that at least afirst zone of a first buried layer of a first conductivity type of thefirst bipolar transistor and a second buried layer of a first or asecond conductivity type of the second bipolar transistor are introducedinto the semiconductor substrate, at least a first collector zone of thefirst bipolar transistor and a first collector zone of the secondbipolar transistor are produced, the first collector zone of the firstbipolar transistor adjoining the first zone and the first collector zoneof the second bipolar transistor adjoining the second buried layer, thefirst collector zone is formed as first conductivity type, a secondcollector zone is produced on the first collector zone of the secondbipolar transistor and a second collector zone is produced on the firstcollector zone of the first bipolar transistor, and at least oneinsulation region is produced, which isolates at least the collectorzones from one another.

This too means that it is possible, in a simple manner, for collectorregions to be fabricated which have both different thicknesses and sharpprofiles with a steep gradient with respect to the adjacent buriedlayers and, consequently, a transistor structure is formed whichcomprises both the properties of an HV transistor and those of an HFtransistor.

A development of the methods according to the invention provides for thethird collector zone to be deposited.

In a preferred development of the methods according to the invention,the third collector zone is deposited epitaxially. As a result of this,the collector zone is grown with the fewest possible crystal defects,which is very important for the functional properties of a bipolartransistor.

Another refinement provides for an insulating layer (SOI layer,SOI—Silicon On Insulator) to be provided between the buried layers andthe semiconductor substrate. The collector regions are therebyelectrically insulated and capacitively decoupled from the substratewithout the need for any additional insulation.

Typically, the insulation region which isolates at least the collectorregions from one another is isolated from one another with the aid ofshallow trench isolation technology (STI technology). The insulationregion may be filled with an electrically insulating material, such as aCVD oxide (CVD=Chemical Vapor Deposition), for example. Preferably, thetwo laterally adjacent highly doped buried layers of two bipolartransistors are thereby electrically insulated from one another. Saidinsulation region may be embodied for example as a full trench or as adeep trench.

A full trench is a trench, for example between components of a chip, inwhich the silicon is etched or interrupted as far as the buried layers,so that current paths between the components are completely interrupted.A full trench can isolate relatively large transistor regions from oneanother, as is also described in an article by S. Maeda, “Impact of 0.18μm SOI CMOS Technology using Hybrid Trench Isolation with HighResistivity Substrate on Embedded RF/Analog Applications”, 2000 Symp. onVLSI Technology—Digest of Technical Papers (CAT. No. 00CH37104), pages154 to 155.

A deep trench is described for example in the article “An SOI-Based HighPerformance Self-Aligned Bipolar Technology Featuring 20 ps Gate-Delayand a 8.6 fJ Power Delay Product” by E. Bertagnolli et al., 1993, Symp.on VLSI Technology, Digest of Technical Papers (CAT. No. 93CH3303-5),pages 63 to 64. In contrast to the full trench, the deep trench is notwide enough to be able to integrate the entire dimensions of passivecomponents above it. Rather, the deep trench serves for dielectriccomponent isolation.

Preferred exemplary embodiments of the present invention are explainedin detail below with reference to the accompanying drawings, in which

FIGS. 1 a to 1 d show a diagrammatic cross-sectional view of a firstmethod according to the invention for producing a transistor structureaccording to the invention with two collector regions having a differentcollector width by means of selective epitaxy,

FIGS. 2 a to 2 e show a diagrammatic cross-sectional view of a secondmethod according to the invention for producing a transistor structurewith two collector regions having a different collector width by meansof whole-area epitaxy,

FIGS. 3 a to 3 c show a diagrammatic cross-sectional view of a thirdmethod according to the invention for producing a transistor structurewith two collector regions having a different collector width,

FIG. 4 shows a diagrammatic cross-sectional view of an alternativeconfiguration for producing a transistor structure with two collectorregions having a different collector width with an SOI structure.

The first method according to the invention for producing a transistorstructure according to the invention with two collector regions having adifferent collector width which is described below with reference toFIGS. 1 a to 1 d is performed by means of selective epitaxy.

In FIG. 1 a, the, for example n⁺-doped, buried layers 5.1 and 5.2 havealready been introduced into the semiconductor substrate 1 and insulatedfrom one another by insulation regions 4, here realized as deep trenches4. The semiconductor substrate 1 comprises e.g. monocrystalline siliconwhich is p-doped.

A first auxiliary layer 6 and a second auxiliary layer 7 are furthermoreprovided, which isolate the insulation region 4 from the semiconductorsubstrate 1 and the buried layers 5.1 and 5.2. In this case, the secondauxiliary layer 7 adjoins the insulation region 4 and the firstauxiliary layer 6 adjoins the second auxiliary layer 7 and also thesemiconductor substrate 1 and the buried layers 5.1 and 5.2.

The second auxiliary layer 7 preferably comprises a material which isresistant to oxidation and can be etched selectively with respect tooxide, such as silicon nitride Si₃N₄, for example. This makes itpossible to avoid sidewall defects, that is to say crystal defects whicharise at the interface between a dielectric material and silicon duringthe epitaxial growth of the silicon. In another variant, the secondauxiliary layer 7 may be formed from polysilicon. The thickness of saidsecond auxiliary layer 7 lies in the range of between 3 nm and 60 nm.One advantage of this thin nitride lining is that it protects the wallof the insulation region 4, which is filled with CVD oxide, for example,against oxidations and thus prevents defect formations.

The first auxiliary layer 6 preferably comprises a material which can beetched selectively with respect to the layer 7 and avoids largemechanical stresses on the semiconductor substrate 1, such as an oxide,for example. Furthermore, the auxiliary layer 6, up to the epitaxy, canprotect the sensitive silicon surface of the buried layers 5.1 and 5.2against oxidation.

The openings 12 are etched into an STI oxide layer 13 down to the secondauxiliary layer 7, which STI oxide layer preferably covers the wholearea of the semiconductor substrate 1 with the auxiliary layers 6 and 7situated thereon. As is known from EP 0 600 276 B1, the etching may beeffected by anisotropic dry etching which stops selectively on siliconnitride, and thus on the second auxiliary layer 7.

In the subsequent method step in accordance with FIG. 1 b, a lateralundercut 14 of the auxiliary layers 6 and 7 is effected. The undercut 14is described in more detail in EP 0 600 276 B1. Since sidewall defectsform proceeding from the interfaces between the auxiliary layers 6 and 7and the surface of the buried layers 5.1 and 5.2 and grow up at an angleof about 52° along (111) crystal faces, that is to say for example alongthe sidewall of the STI oxide layer, this growth of the sidewall defectscan be interrupted by the overhang formed by the undercuts 14 of the STIoxide layer 13.

Afterward, a first collector region 2.1 having a thickness C1 and also acollector zone 2.2.1 having a thickness C3 are deposited epitaxially,the first collector region 2.1 adjoining the first buried layer 5.1 andthe collector zone 2.2.1 adjoining the second buried layer 5.2. In thiscase, the collector zone 2.2.1 is provided for the second collectorregion of a second bipolar transistor. The thicknesses C1 and C3 of thecollector region 2.1 and of the collector zone 2.2.1 are approximatelyidentical and are preferably between 50 nm and 300 nm.

After the first collector region 2.1 has been covered with a maskinglayer 8, a further collector zone 2.2.2 is applied epitaxially on thecollector zone 2.2.1 in FIG. 1 c. Said collector zone 2.2.2 preferablyhas a thickness C4 of between 100 nm and 200 nm. The collector width C2of the second collector region 2.2, composed of the collector zones2.2.1 and 2.2.2, thus lies in the range of between 150 nm and 500 nm.

In the present example, the second collector region 2.2 terminates atapproximately the same level with the surface of the STI oxide layer 13.

Typically, the collector width C1 of the first collector region 2.1 andthe collector width C2 of the second collector region 2.2 are in a ratioof between 0.05 and 0.9 to one another. Typical values are 100 nm forthe collector width C1 and 250 nm for the collector width C2. Thedifferent collector widths C1 and C2 of the two collector regions 2.1and 2.2 on the same semiconductor substrate 1 have the effect ofoptimizing the properties both of an HF transistor and of an HVtransistor.

If the intention is to obtain even greater differences between thecollector widths of the first and second collector regions 2.1 and 2.2,then, in the method step of FIG. 1 b, the collector width C1 and thethickness C3 are kept relatively low and, in the subsequent method stepof FIG. 1 c, the deposition of the collector zone 2.2.2 with a secondthickness C4 is repeated appropriately often.

In the transistor structure of FIG. 1 d, the masking layer above thecollector region 2.1 has been removed and collector terminal regions 11have been introduced. After filling with tungsten, for example, thecollectors can be routed out electrically to the surface, therebyenabling the transistor structure to be integrated into an integratedcircuit.

The method according to the invention for fabricating a transistorstructure for two bipolar transistors with the aid of selective epitaxywhich has been described with reference to FIGS. 1 a to 1 d isparticularly simple. The various collector regions are deposited inrespectively successive epitaxy steps with the required thickness in theSTI oxide layer 13, the already completed collector region 2.1 beingcovered by a masking layer 8 in order to prevent a further epitaxialdeposition. The regions in the STI oxide layer 13 which are required foran epitaxial deposition are thus opened in each case only for thecorresponding epitaxy step.

It is also possible with the aid of whole-area epitaxy to realizecollector regions 2.x having different collector widths and sharpjunctions with respect to the highly doped buried layers, as explainedbelow with reference to FIGS. 2 a to 2 e. In this case, the collectorregions 2.x terminate toward the top in planar fashion at the same levelwith the surface of the STI oxide layer 13, the thicknesses D1 and D2 ofthe buried layers 5.1 and 5.2 being varied. This planar termination isparticularly advantageous since planar surfaces are required forsubsequent photosteps (not described here), with feature sizes of lessthan 0.35 μm.

In accordance with FIG. 2 a, an epitaxial layer 9 having a thickness E1is deposited over the whole area of the semiconductor substrate 1, intowhich a first zone 5.1.1 of a first buried layer and a further firstzone 5.2.1 of a second buried layer have already been implanted. Thefirst zones 5.1.1 and 5.2.1 are preferably n⁺-doped.

Afterward, in FIG. 2 b, a second zone 5.1.2 of the buried layer 5.1 anda second zone 5.2.2 of the buried layer 5.2 are introduced into theepitaxial layer 9, these second zones 5.x.2 also being n⁺-doped. In thiscase, the second zone 5.1.2 extends approximately over the area of thefirst zone 5.1.1, whereas the second zone 5.2.2 of the buried layer 5.2merely extends over a partial region of the first zone 5.2.1 of theburied layer 5.2.

In the subsequent step of the method according to the invention in FIG.2 c, a second epitaxial layer 10 is deposited with a thickness E2 overthe whole area of the epitaxial layer 9 and the second zones 5.x.2 ofthe buried layers 5.1 and 5.2. In this case, said second epitaxial layer10 may result from a single deposition or a plurality of depositions insuccession. The collector width C1 of a first collector region may bedefined by the thickness E2 of said epitaxial layer 10, the collectorwidth C1 corresponding to the thickness E2 of the epitaxial layer 10. Bycontrast, the collector width C2 of the second collector regioncorresponds to the sum of the thicknesses E1 of the epitaxial layer 9and the thickness E2 of the epitaxial layer 10.

In FIG. 2 d, the buried layers 5.1 and 5.2 are insulated from oneanother by means of insulation regions 4, embodied as deep trenches inthe present example.

Afterward, in FIG. 2 e, the STI oxide layer 13 is etched into theepitaxial layer 10 in accordance with FIG. 2 d and preferably filledwith STI oxide, regions for the collector terminal region 11 and alsothe first and second collector regions 2.1 and 2.2 being left free. Thecollector terminal regions 11 are then etched above the second zones5.2.2 and 5.1.2 in order thereby to enable an electrical linking of thecollector.

The first collector region 2.1 thus has a first collector width C1 andthe second collector region has a larger collector width C2. The twocollector regions 2.1 and 2.2 terminate in planar fashion with thesurface of the STI oxide layer 13 and both have sharp junctions betweenthe heavily doped regions of the buried layers 5.x and the more lightlydoped collector regions 2.x. As a result of this, the transistorstructure acquires defined and exactly determinable properties.

A further method according to the invention for fabricating a transistorstructure according to the invention with two collector regions having adifferent collector width is described in more detail with reference toFIGS. 3 a to 3 c.

In FIG. 3 a, analogously to FIG. 1 b, provision is made of a structurehaving a, preferably p-doped, semiconductor substrate 1, a first zone5.1.1 of a first buried layer implanted into the semiconductor substrate1, and an implanted second buried layer 5.2, having a thickness D2,insulation regions 4, a first auxiliary layer 6 and a second auxiliarylayer 7, an STI oxide layer 13 and the collector zones 2.1.1 and 2.2.1.

As in FIG. 1 b, in FIG. 3 a, the auxiliary layers 6 and 7 are undercutunder the STI oxide layer 13, so that the collector zones 2.1.1 and2.2.1 have a stepped profile in cross section. By virtue of thisundercut 14, the STI oxide layer 13 exhibits an overhang over part ofthe collector zones 2.1.1 and 2.2.1.

The thickness C3 of said collector zones 2.1.1 and 2.2.1 may varybetween 5 nm and 300 nm.

After a masking layer 8 has been applied to the region of the collectorzone 2.2.1, the collector zone 2.1.1, as shown using the arrows 15 inFIG. 3 b, is doped in such a way that it has the same doping as thefirst zone 5.1.1 of the first buried layer 5.1. This is preferably ann⁺-type doping. This newly formed second zone 5.1.2 and the first zone5.1.1 now form the buried layer 5.1 having a thickness D1.

After the removal of the masking layer 8, in FIG. 3 c, a first collectorregion 2.1 is deposited epitaxially on the first buried layer 5.1 with acollector width C1 and a further collector zone 2.2.2 having a thicknessC4 is deposited epitaxially on the collector zone 2.2.1. The secondcollector region 2.2 is now formed from the two collector zones 2.2.1and 2.2.2 and has a collector width C2 representing the sum of thethicknesses C3 and C4. Both collector regions 2.1 and 2.2 terminate inplanar fashion with the surface of the STI oxide layer 13.

After the introduction of the collector terminal regions 11 and fillingwith tungsten, for example, the transistor structure of FIG. 3 c issuitable for use in bipolar transistors.

In a further embodiment according to the invention as shown in FIG. 4,an insulating layer 3 is produced between the semiconductor substrate 1and the buried layers 5.1 and 5.2.

The production of the collector regions 2.1 and 2.2 having differentcollector widths C1 and C2 and sharp junctions between the collectorregions and the buried layers may correspond to the method according tothe invention from FIGS. 3 a to 3 c. Moreover, the methods according tothe invention which have been explained with reference to FIGS. 1 a to 1d and 2 a to 2 e are also conceivable.

Preferably, in the methods according to the invention as shown in FIGS.1 to 4, the first buried layer 5.1 and the second buried layer 5.2 areconfigured as an identical conductivity type. This configuration makesit possible to form two transistor structures of identical type onebeside the other, that is to say for example two npn transistors or twopnp transistors.

In an alternative embodiment, the first buried layer 5.1 and the secondburied layer 5.2 are configured as different conductivity types. Thismakes it possible to form an npn transistor beside a pnp transistor onthe same semiconductor substrate 1.

In a particularly advantageous development of the methods according tothe invention, the collector regions are formed with a dopant gradient,the concentration of the dopant varying in the horizontal direction.This development makes it possible, for example, to form an increaseddopant concentration in the central collector region. This development,in particular with a small thickness of the collector region, reducesthe base-collector space charge zone and thus reduces the collectortransit time. This development is particularly advantageous primarily inthe case of very small transistor structures in which the emitter regionis arranged centered above the collector region.

It goes without saying that, instead of the deep trenches, it is alsopossible to use full trenches as insulation regions 4.

Overall, the methods according to the invention as explained withreference to FIGS. 1 to 4 make it possible to fabricate transistorstructures having a first collector region 2.1, having a first collectorwidth C1, and also a second collector region 2.2, having a largercollector width C2, on the same semiconductor substrate 1, all junctionsbetween differently doped regions having a sharp interface. In thiscase, by way of example, the first collector region 2.1 is suitable fora high-frequency transistor with high limiting frequencies f_(T) and thesecond collector region 2.2 is suitable for a high-voltage transistorwith increased breakdown voltages.

1. A method for fabricating a transistor structure comprising at least afirst and a second bipolar transistor having different collector widths,the method comprising: A) providing a semiconductor substrate, B)introducing at least a first buried layer of the first bipolartransistor and a second buried layer of the second bipolar transistorinto the semiconductor substrate, and C) producing at least a firstcollector region having a first collector width on the first buriedlayer and a second collector region having a second collector width onthe second buried layer, wherein a) for the production of the secondcollector width, a first collector zone having a first thickness isproduced on the second buried layer, and b) a second collector zonehaving a second thickness is produced on the first collector zone, andc) at least one insulation region is produced which isolates at leastthe collector regions from one another.
 2. A method for fabricating atransistor structure comprising at least a first and a second bipolartransistor having different collector widths, the method comprising: A)providing a semiconductor substrate, and B) producing at least a firstcollector region of the first bipolar transistor having a firstcollector width and a second collector region of the second bipolartransistor having a second collector width, wherein a) at least a firstzone of a first buried layer of a first conductivity type of the firstbipolar transistor and a first zone of a second buried layer of a firstor a second conductivity type of the second bipolar transistor areintroduced into the semiconductor substrate, b) a first epitaxial layeris produced, which covers, over the whole area, at least the firstzones, c) at least a second zone of the first conductivity type isproduced within the first epitaxial layer, the second zone adjoining thefirst zone of the first buried layer, d) a second epitaxial layer isproduced, which covers, over the whole area, at least the firstepitaxial layer and the second zone of the first buried layer, d) atleast one insulation region is produced which isolates at least thecollector regions from one another, and e) the second zone of the firstburied layer adjoins the first collector region and the first zone ofthe second buried layer adjoins the second collector region.
 3. A methodfor fabricating a transistor structure comprising at least a first and asecond bipolar transistor having different collector widths, the methodcomprising: A) providing a semiconductor substrate, and B) producig atleast a first collector region of the first bipolar transistor having afirst collector width and a second collector region of the secondbipolar transistor having a second collector width, wherein a) at leasta first zone of a first buried layer of a first conductivity type of thefirst bipolar transistor and a second buried layer of a first or asecond conductivity type of the second bipolar transistor are introducedinto the semiconductor substrate, b) at least a first collector zone ofthe first bipolar transistor and a first collector zone of the secondbipolar transistor are produced, the first collector zone of the firstbipolar transistor adjoining the first zone and the first collector zoneof the second bipolar transistor adjoining the second buried layer, c)the first collector zone is formed as the first conductivity type, d) asecond collector zone is produced on the first collector zone of thesecond bipolar transistor and a second collector zone is produced on thefirst collector zone of the first bipolar transistor, and e) at leastone insulation region is produced, which isolates at least the collectorzones from one another.
 4. The method as claimed in claim 1, wherein thesecond collector zone is deposited.
 5. The method as claimed in claim 4,wherein the second collector zone is deposited epitaxially.
 6. Themethod as claimed in claim 1, wherein an insulating layer is producedbetween the semiconductor substrate and the buried layers.
 7. The methodas claimed in claim 1, wherein the insulation region is produced withthe aid of shallow trench isolation technology.
 8. The method as claimedin claim 2, wherein the second collector zone is deposited.
 9. Themethod as claimed in claim 8, wherein the second collector zone isdeposited epitaxially.
 10. The method as claimed in claim 2, wherein aninsulating layer is produced between the semiconductor substrate and theburied layers.
 11. The method as claimed in claim 2, wherein theinsulation region is produced with the aid of shallow trench isolationtechnology.
 12. The method as claimed in claim 3, wherein the secondcollector zone is deposited.
 13. The method as claimed in claim 12,wherein the second collector zone is deposited epitaxially.
 14. Themethod as claimed in claim 3, wherein an insulating layer is producedbetween the semiconductor substrate and the buried layers.
 15. Themethod as claimed in claim 3, wherein the insulation region is producedwith the aid of shallow trench isolation technology.